Some types of semiconductor logic gates show a strong temperature dependence. This effect has proved to be particularly a problem in logic gates which use gallium arsenide (GaAs) depletion mode MESFETs but also may arise in other instances. The result of this temperature dependence is to limit the temperature range over which such logic gates may be used. This limited temperature range is much less than the full military temperature range of -55.degree. C. to +125.degree. C. for some logic families. In order to obtain logic gates of such families which can operate over this entire range, temperature compensation is required. The present invention provides a temperature compensation system.
In typical GaAs circuits such as Schottky Diode FET Logic (SDFL), Buffered FET Logic (BFL), Source Coupled FET Logic (SCFL), and input and output buffers, logic level shifting is achieved by Schottky diodes connected in series with a current source. FIG. 1 shows a typical level shifting circuit employing a Schottky diode 10 in series with an FET 20. Circuits of the type shown in FIG. 1 are of limited utility over wide temperature ranges because the negative temperature coefficient of the Schottky diode voltage drop adds to the negative temperature coefficient of the FET threshold voltage, V.sub.T. Schottky diodes and MESFETs typically have temperature coefficients on the order of -1.1 mV/.degree.C. and -1.3 mV/.degree.C., respectively. Consequently, the noise margin of the circuit deteriorates rapidly with temperature variations. SDFL gate arrays implemented with standard Schottky diode level shifters can be expected to work only over a temperature range of about -35.degree. C. to about +73.degree. C.